Novel Twin-Gate Design Paves Way for Ultra Low Power 3D Devices

IME researchers have described for the first time the realisation of true 3-D integration by twin-gate metal-oxide-semiconductor field-effect transistors (MOSFET) on a single vertical Si nanowire. The devices are fabricated by CMOS processes and they exhibit >106 ON/OFF ratio, tunability in drain current, as well as ‘AND’ gate functionality with 50% area reduction. The twin-gate device design is promising as an integral platform for enabling ultra low power and feature-packed 3D functional devices and circuits.

Reference:

Xiang Li et. al., “Vertically stacked and independently controlled twin-gate MOSFETS on a single Si nanowire" IEEE Electron Device Letters, Vol 32, pg 1482 - 1494, 2011