SpEED Capabilities

The SpEED program has many well-established capabilities for achieving its proposed scientific and technological objectives. The proposed effort strategically integrates our established capabilities in the areas of 1) Materials and Device Development, 2) Microscopy and Modelling, 3) Electrical Transport Measurements, and 4) 200 mm wafer-level scaling. Importantly, the fabrication and translational components utilise a well-established 200 mm semiconductor fabrication platform which has been successfully used for multiple industry collaborations. The programme provides many pathways for near-term engagement with local foundries and chip manufacturers, and long-term capabilities for sustained value capture in the burgeoning field of edge computing.

Materials & Device Development:
(a) Film Deposition
  • Custom-designed ChironTm PVD system consisting of 8 DC and 2 RF targets, with built-in in-situ atomic layer deposition system, for film deposition on 100 mm wafers and coupons with sub-Å precision
(b) Film Characterisation
  • Magnetic analysis using vibrating sample magnetometer (VSM Model EZ11), alternating gradient magnetometer (MicroMag Model 2900) and superconducting quantum interference device (SQUID MPMS)
  • Structural/electronic/chemical analysis using x-ray diffraction (BrukerTM 2D Micro, PANalytical X’PertTM), x-ray reflectivity, x-ray photoelectron spectrometry (Theta Probe XPS) and ellipsometry
  • Electrical analysis using Capres current-in-plane tunneling tool to determine film level tunnelling magnetoresistance and resistance-area with magnetic fields up to 0.6 T
  • Imaging analysis using atomic force and magnetic force microscopy, transmission electron microscopy, scanning electron microscopy elaborated in the following section
(c) Device Fabrication
  • Lithography tools such as EVG™ mask aligner and Elionix™ electron beam lithography (EBL) system with ~1.5 μm and ~10 nm resolution, respectively
  • Reactive ion etch (IntlVacTM) for milling
  • Thermal/electron beam evaporators (EvoVacTM) for metallisation

Microscopy & Modelling:
  • Atomic force and magnetic force microscopy (DI 3100 SPM & Bruker ICONTM) capable of producing non-perturbative, high contrast and spatial resolution images.
  • Transmission electron microscopy (JEOL 2100 TEM/Philips CM300 FEGTEM) giving high resolution cross-sectional images for determining spacer roughness, stack thickness, cell profile, as well as elemental mapping of individual layers using energy dispersive x-ray analysis and electron energy loss spectroscopy. The FEI TitanTM is also equipped with Lorentz and holography capabilities for analysing magnetic textures at variable fields and temperatures.
  • Magnetic transmission x-ray microscopy at the XM1 beamline in Lawrence Berkeley National Laboratory, USA, with full field transmission x-ray magnetic circular dichroism contrast, for imaging magnetic textures with ~30 nm resolution deposited on thin membranes.
  • Device and circuit design modelling (e.g. MuMaX3, OOMMF, VASO, SPICE) leveraging on Petascale supercomputing facilities at the National Supercomputing Centre (NSCC).

Electrical Transport Measurements:
  • Custom-made electrical device testing platforms and probe stations with pulsing capabilities <1 ns and noise levels down to ~1nV
  • Cryostats and physical property measurement system for low temperature magneto-transport measurements (2 K, 9 T)
  • ISI Wafer auto-prober capable of conducting device testing modules including TMR, switching voltage, endurance, write error rate, read error rate, breakdown voltage
  • Custom-made high resolution broadband and spin-torque ferromagnetic resonance systems with frequency range of 67 GHz in magnetic fields up to 1 T and variable temperature operation 

200 mm Wafer-Level Scaling:
(a) Device Stack Deposition Tool
  • Singulus Timaris cluster sputtering system with pre-cleaning, annealing, wedge deposition and multi-target (over 20) process modules at 2 Å thickness uniformity
(b) Copper Protocol Fabrication Line
  • Spin coating & developing using Silicon Valley Group SVG 90S
  • Lithography using Canon EX5 248 nm DUV Stepper
  • Hard mask etch using advanced dielectric etcher (SPTS Etch system) or induced coupled plasma (ICP)-fluorine based chemistry etching (Oxford PlasmaPro System 100 cobra ICP)
  • Cell etch using Oxford Ionfab 300Plus (Ion milling)
  • Cell passivation and insulation using OIPT Plasmalab System 380
  • Descum using Axcelis Ashing System
  • Chemical mechanical polishing using Okamoto SPP600S
  • Electrode deposition using Singulus Rotaris Cluster System or AMAT Endura System
  • Annealing using horizontal annealing furnace
(c) Prototyping
  • Simulation packages including industry standard Verilog-A, electronic design automation (EDA) and computer aided drafting (CAD) for the design of a viable integrated circuit consisting of a microscopic electronic circuit array of SOT-based devices
  • Simulated IC designs implemented on testing platform such as field programmable gate arrays (FPGA) and printed circuit boards (PCB) and tested on high speed and precision analogue/digital characterisation circuits and device specific read/write circuits

Key Contacts

Dr. Anjan Soumyanarayanan
Dr. Lim Sze Ter 

Last update : 2/11/2019 9:34:58 AM