The STT-MRAM program focuses on developing high performance STT-MRAM devices with low power consumption, high speed and long endurance.
The STT-MRAM program consists of three teams: material and structure design, process development and testing. The material and structure design team focuses on new STT-MRAM cell stack design to achieve low current density, large signal to noise ratio and high writing/reading speed. The process development team works to deliver sub-50nm STT-MRAM devices with high yield and uniformity. The back end process development with complementary metal–oxide–semiconductor (CMOS) technology is another important mission for process development team. The testing team uses an advance testing setup to evaluate STT-MRAM parameters and working performance and provides feedback to the design team. The three teams have different focuses but work closely to support each other in order to develop successful STT-MRAM technology.
Fig. 1 STT-MRAM Program Structure
The following figure shows a stack structure of a recent developed magnetic tunnel junction (MTJ), which is the core part of an STT-MRAM device. The achieved TMR based on such stack structure is more than 240% with RA as low as 18Oµm2, which is among the best results.
Fig. 2 STT-MRAM MTJ stack structure
Capability and Future Plan
Currently, sub-100nm STT-MRAM device can be fully fabricated in a completed 8-inch line, and some of these tools will be 12-inch capable. Future STT-MRAM stack will be developed in 23-target Singulus sputtering system, which is also 12-inch compatible. Further SOT-MRAM stack will be developed as well.