1 March 2007
IME's invention - a method of forming through-wafer interconnects for vertical wafer level packaging - was cited in Semiconductor International (March, 2007). This invention was issued the U.S. patent in February 2007.
Through-wafer via interconnects are a critical technology for 3-D stacking of electronic and MEMS chips. The via is filled by electroplating process using a sacrificial wafer bonded to the through hole via wafer. The normal method of separating the sacrificial wafer is by backgrinding which requires an expensive backgrinding machine.
Backgrinding is a mechanical process and may generate defects in the actual through hole via wafer. IME researchers have developed a through-hole filled via wafer which eliminates the need for the backgrinding process, hence making the wafer more robust. Since this invention removes one process in fabrication, it reduces the cost as well. The developed package format is suitable for MEMS and RF applications.