3 November 2010
Eight IME papers have been accepted for this year’s IEEE Asian Solid-State Circuits Conference (A-SSCC 2010), the highest number among all participating private corporations, research institutes and academic institutions.To be held at the Crowne Plaza Park View Wuzhou Beijing, China from November 8 to 10, A-SSCC 2010 is an internationally-recognised forum for presenting cutting-edge research and exchanging innovative ideas in the solid-state and semiconductor fields. Reflecting the diversity of areas that IME conducts its research in, the institute will be presenting on a varied range of topics, spanning across four sessions:
A 5.9mW 50Mbps CMOS QPSK/O-QPSK Transmitter Employing Injection Locking for Direct Modulation
Shengxi Diao, Yuanjin Zheng, Yuan Gao, Xiaojun Yuan and Minkyu Je - Institute of Microelectronics, A*STAR; Chun-Huat Heng -Department of Electrical and Computer Engineering, National University of Singapore
A CMOS MedRadio Receiver RF Front-End with Complementary Current-Reuse LNA for Biomedical Applications
— A 900MHz QPSK/O-QPSK transmitter suitable for biomedical high quality imaging application is presented. The phase modulation is achieved by directly modifying the self-resonant frequency of a sub-harmonic injection-locked oscillator through capacitor bank switching. Due to the simplicity of the proposed architecture, implemented in 0.18μ
m CMOS technology, it consumes very low power of 3mW and 5.88mW with 1.2V and 1.4V supply voltages respectively, while transmitting at 50Mbps data rate. The transmitter can deliver output power of -3.3dBm at 1.4V supply with an EVM of 6.6%.
A 18 mW Tx, 22 mW Rx Transceiver for 2.45 GHz IEEE 802.15.4 WPAN in 0.18-mm CMOS
M. Kumarasamy Raja, Xuesong Chen, Yan Dan Lei, Zhao Bin, Ben Choi Yeung and Yuan Xiaojun - Institute of Microelectronics, A*STAR
Abstract— This paper demonstrates a highly integrated transceiver for 802.15.4, consuming a dc power of 18 mW and 22.3 mW in the Tx and Rx mode respectively, which is the lowest reported so far. The gm boosted LNA shares the dc current with mixer, complex filter uses transistorized biquads, Limiting Amplifier and RSSI chain uses two local loops to save dc power. In the Tx, 2-point direct FSK modulation using normal sized varactors are used in the PLL, which not only obviates the need for auto calibration but also saves dc power due to the absence of DAC. The low IF receiver achieves a sensitivity of -94 dBm, an over load point of -20 dBm adjacent and alternate channel rejections of 40 dB and 55 dB respectively and a linear RSSI range of 89 dB. The transmitter delivers an OQPSK modulated signal of 0 dBm, with an EVM of 7% and the output spectrum meets the mask requirements of 802.15.4, FCC & ETSI. Implemented in 0.18-μm CMOS, loop filter and the crystal resonator for the PLL are the only external components apart from the decoupling capacitors.
Hyouk-Kyu Cha, M. Kumarasamy Raja, Xiaojun Yuan, and Minkyu Je - Institute of Microelectronics, A*STAR
Abstract — An ultra-low-power 401-406 MHz Medical Device Radiocommunication Service (MedRadio) receiver RF front-end for biomedical telemetry applications is implemented using 0.18-μm CMOS technology with a 1-V supply voltage. The receiver RF front-end employs the proposed complementary current-reuse low-noise amplifier (CCRLNA) which shows enhanced noise and linearity performance in comparison to the well-known source degeneration cascode LNA at equal power consumption and design conditions. The RF front-end including the proposed CCRLNA, transconductor, I/Q folded mixer, and LO buffers achieves a conversion gain of 28.7 dB, NF of 5.5 dB, and IIP3 of -25 dBm while consuming less than 500μW from a 1-V supply voltage and occupying 0.7mm2 of core die area.
A Tactile Sensor ASIC for a Sensorised Guidewire in Minimally Invasive Surgical Operations
Kok Lim Chan, Kei-Tee Tiew, Andreas Astuti Lee, Jianwen Luo, Simon Sheung Yan Ng and Minkyu Je - Institute of Microelectronics, A*STAR
Abstract — In this paper, a tactile sensor ASIC for a Sensorised guidewire in minimally invasive surgical operations is presented. This ASIC interfaces with Silicon Nanowire (SiNW) sensors, which capture the force exerted at the tip of the guidewire and present it as a resistance value. The resistance is then converted to current pulses in the ASIC. These pulses are transmitted and displayed on an external monitoring module through a 3-wire interconnect, which is also used to carry the control signals and the power supplies for the ASIC. There are three major challenges: limited area due to the integration at the tip of the guidewire together with the sensors, restricted number of interconnecting wires through the guidewire, and huge resistance variations in the SiNW sensors. These challenges are addressed through an incremental double sampling second-order single-OTA ΔΣ ADC, a 3-wire interface with the external module, and a programmable analog front-end, respectively. The chip has been fabricated in 0.18�m CMOS and occupies an area of only 500�m x 650�m. A 7-bit resolution is achieved for the sensor resistance ranging between 20KΩ and 800KΩ, with an overall power consumption of only 250�W.
A 21.6µW Inductively Powered Implantable IC for Blood Flow Measurement
Pradeep Basappa Khannur, Kok Lim Chan, Jia Hao Cheong, Kai Kang, Andreas Astuti Lee, Xin Liu, Huey Jen Lim, Kotlanka Ramakrishna and Minkyu Je - Institute of Microelectronics, A*STAR
Abstract — This paper presents a fully integrated inductively powered implantable circuits for blood flow measurement, which are embedded within vascular prosthetic grafts for early detection of graft degradation or failure. The ASIC interfaces with micro-fabricated pressure sensors and uses a 13.56MHz carrier frequency for power transfer and command/data communication. A backscatter-modulated passive telemetry is used for transmitting sensor readout information to an external monitoring device. The chip has been fabricated in 0.18μm CMOS process, occupies a total active area of 1.5x1.78mm2 and consumes a total power of 21.6μW. The rectifier achieves an efficiency of 66%. The sub-μW 10-bit SAR ADC achieves an ENOB of 8.5 bits at 106KS/s conversion rate.
130-GHz Gain-Enhanced SiGe Low Noise Amplifier
Bo Zhang1,2,3, Yong-Zhong Xiong2, Lei Wang2, Sanming Hu2, Teck Guan Lim2, Yi-Qi Zhuang1, Le-Wei Li3 and Xiaojun Yuan2 — 1Xidian University, Xi’an, China; 2Institute of Microelectronics, A*STAR; 3National University of Singapore
Abstract — A 130 GHz low noise amplifier (LNA) in 0.13-μm SiGe BiCMOS technology has been designed and characterised. The gain-boosted cascode topology with 3D grounded-shielding structures is employed. The results showed that the LNA with a chip area of 400μm � 900μm achieved gain of ~17.5 dB with a 3 dB bandwidth of ~25 GHz and noise figure of ~7.7 dB at 130 GHz with total dc power consumption of 31.5 mW was demonstrated.
A 60 GHz Heterodyne Quadrature Transmitter with a New Simplified Architecture in 90nm CMOS
James Brinkhoff1,2, Fujiang Lin1,3, Kai Kang1,4;, Duy-Dong Pham1 and Chun-Huat Heng5 — 1Institute of Microelectronics, A*STAR; 2Sapphicon Semiconductor, Sydney; 3University of Science and Technology of China; 4University of Electronic Science and Technology of China; 5National University of Singapore
Abstract — A 60 GHz heterodyne up-convertor consuming only 29 mW, together with a PA consuming 84 mW, is presented. It is implemented in 90nm CMOS. It takes advantage of sub-harmonic mixing and a sliding IF architecture, using a single LO around the relatively low frequency of 20 GHz, thus relaxing millimetre-wave LO design. This also allowed LO buffers to be eliminated, which minimizes area and power consumption. The I/Q up-converter includes a quadrature VCO, resistive IF mixers, IF amplifier and RF sub-harmonic mixer. It achieves a tuning range of 8.8 % and a conversion gain of 13.1 dB. The 60 GHz power amplifier delivers 9.8 dBm, has 9.7 % PAE and 20 dB gain.
118-dB Dynamic Range, Continuous-Time, Opened-Loop Capacitance to Voltage Converter Readout for Capacitive MEMS Accelerometer
Kevin T. C. Chai1
, Dong Han1
, Ravinder P. Singh1
, Duy D. Pham1
, Chin Y. Pang1
, Jian W. Luo1
, David Nuttman2
and Minkyu Je1
Institute of Microelectronics, A*STAR; 2
Physical Logic Ltd
Abstract — A high performance analog front-end (AFE) interface circuit for capacitive MEMS accelerometer is presented in this paper. The AFE was implemented in a continuous-time (CT), chopper stabilized, capacitance to voltage converter (CVC) topology with a variable gain amplifier (VGA) for greater flexibility and a low pass filter (LPF) which limited the signal bandwidth to 300 Hz. Noise analysis of each building block of the AFE is also presented in this paper. The measured input referred noise density is 27 nV/. Long term stability results showed that the input offset has an Allan deviation floor of 60 nVrms. The nonlinearity for the AFE was measured at �1 %.