10 April 2008
The IME's Nanoelectronics team has won the prestigious 2007 IEEE Electron Devices Society George E. Smith Award for its ground breaking work on "Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors" published in the IEEE Electron Device Letters, Vol.28, No.3, pp. 211-213, March 2007. This annual award recognizes the best paper published in IEEE EDL in 2007 which will be presented on December, 15 at the 2008 IEEE International Electron Devices Meeting (IEDM) to be held in San Francisco.
Just last year in November, IME and Unisantis (Japan) captured the world's attention with the announcement to co-develop next generation high performance vertical transistors which could revolutionize the semiconductor industry and overcome the predicted end of Moore's Law scaling using state-of-the-art CMOS technology. This accolade echoes the pioneering work at IME and impact to both the research community and industry. As Prof. Cor Claeys, the President of IEEE Electron Devices Society, succinctly put it "about 278 articles were published in Electron Devices Letter in 2007, the selection of your paper for the award is a strong endorsement of the quality of the work" in his congratulatory email to the authors on April 10, 2008.
About IME's Si-based Nanaowire Technology: Gate-All-Around (GAA) Transistors
The GAA nanowire devices are the research focus of Nanoelectronics Team in IME, Singapore. These devices are poised take CMOS beyond what the industry predicts that the reign of Moore's Law scaling will come to an end by 2020. However, due to extremely narrow body, drive capability of the GAA nanowire devices per nanowire channel is limited. Adding channels to increase the drive capability using lateral spread is at the cost of silicon estate per device and thus defeats the purpose of scaling. This 2007 work demonstrated a significant technology breakthrough by fabricating GAA transistors with vertically stacked SiGe nanowire arrays as channel bodies. The vertical stacking strategy leads to enhanced drive capability per silicon estate without compromising on the other performance parameters. The excellent device performances were demonstrated in the vertically stacked device configuration just perfectly as in the case of single nanowire which this Singapore team had illustrated in 2006.