11 December 2006
Two papers by IME researchers on silicon nanowire Gate-All-Around (GAA) transistors were highlighted for special mention at the IEEE International Electron Devices Meeting (IEDM 2006), held from 11-13 December in San Francisco, USA.
The first paper on “Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel Orientation and Low Temperature on Device Performance” by Navab Singh et al, deals with the issue of current leakage in transistors. Using a silicon nanowire as the channel to wrap around a gate completely for better control, IME researchers have successfully achieved an ultra-narrow diameter of 3-6 nm silicon nanowires with high drive currents, comparable to typical CMOS devices (2.4 mA/μm for N-FET and 1.3 mA/μm for P-FET).
The second paper, titled “Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around P-MOSFETs”, by L. Bera et al, details a way to make vertically stacked, GAA arrays of SiGe nanowires with good electrical characteristics. Such 3D arrays offer substantial advantages as they take up little space on a chip. The IME team has demonstrated arrays with up to 15 nanowires in as many as four levels, using epitaxy, conventional lithography, Si oxidation and Ge diffusion into Si GAA P-FETs in a three-level stack. The configuration shows excellent DC characteristics and an on/off ratio of 1x107.
In addition to the two highlighted papers on silicon nanowire GAA transistors, IME also presented seven other papers at IEDM 2006, ranking it among the top five organisations in terms of number of papers accepted. These papers were the research results of IME staff and PhD student attachees in the areas of nanoscale transistors, RF-MEMS, device modelling and reliability.