Modeling Methodology for Reducing Wafer Warpage in 3D IC

Wafer warpage is a serious problem in 3-D integrated circuits (IC) fabrication using through-silicon-via (TSV). This paper describes a modeling method for simulating various process conditions leading to TSV wafer warpage. The developed modeling methodology has been verified by experimental data. Findings from the study provide fundamental guidelines for process optimization that reduces wafer warpage induced stress- the root cause of device failure in realising 3-D IC.
 
Reference:
Faxing Che et. al., “Development of Wafer Level Warpage and Stress Modeling Methodology and Its Application in Process Optimization for TSV (Through-Silicon Via) Wafers”,IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 2, Iss. 6, Pg. 944 - 954, 2012