Novel CMOS-Compatible and Cost-Effective Method to Fabricate Silicon-Based Sub-Nanometre Waveguide

IME researchers have developed a novel CMOS-compatible approach to fabricate a sub-100-nm slot waveguide. The approach employs sacrificial spacer layer deposition and etching as a critical step before conventional waveguide etching to realise the high resolution patterns for sub-100nm slot. With this approach, the high-resolution patterns in the waveguide can be fabricated using readily available DUV lithography system instead of expensive Electron Beam Lithography or Focused Ion Beam etching. Using the same approach, a channel-slot coupler is also fabricated. The successful demonstration of the channel-slot coupler and sub-100-nm slot waveguide in a Mach-Zehnder interferometer (MZI) structure validates the viability of the approach for the fabrication of other low dimension photonic devices that require high resolution patternings.

Reference:

Huijuan Zhang et. al., “CMOS-Compatible Fabrication of Silicon-based Sub-100-nm Waveguide with Efficient Channel-Slot Coupler," IEEE Photonics Technology Letters, Vol 24, pg 10-12, 2012