Over the years our team has developed in-depth understanding of spin-transfer torque (STT) switching and proposed novel solutions to improve memory devices performance in particular from the materials and stack design perspectives. STT writing involves applying currents through an oxide barrier of a magnetic tunnel junction (MTJ). The MTJ resistance is determined by the relative magnetisation directions of FL (free layer) and RL (reference layer). The distinct resistance of the two existing states (AP/ P) correspond to storing a binary ‘1’ or ‘0', respectively. The switching process is affected by various factors, such as the current density, the temperature, and the MTJ size, material selections, and process damages etc.1-5 Interestingly, the switching speed is less temperature-dependent in the precessional regime and become highly temperature-dependent in the thermal activation regime1.
One of our recent experimental studies showed non-collinear structure can deliver ∼53% reduction in critical current density in STT switching without compromising on the thermal stability of the devices. This advantage in switching current performance using the non-collinear stack was found to sustain down to ∼20 nm MTJs1.
Figure from Ref  Size dependence of various MTJs against the parameters of (a)TMR (b) switching current (c) thermal stability, and (d) efficiency. The blue colored symbols are for a non-collinear MTJ stack compared against a standard MTJ stack (orange).
Electric Field Assisted Switching
We also explore alternative low power writing schemes in MTJs is by means of voltage-controlled magnetic anisotropy. We demonstrated that electric field (EF) devices can be switched at a record speed of approximately 0.6 ns with write energies as low as 7 fJ. We did a comprehensive study on the role of the free layer thickness in electric-field controlled nanoscale perpendicular MTJs2. The development of EF-controlled MRAM will be relied upon optimisation of voltage-controlled magnetic anisotropy (ξ) and voltage modulation of coercivity (Hc). Numerous simulation and modelling works have been done, for example, we investigated the possibility of enhancement of voltage-controlled magnetic anisotropy by inserting of an oxide monolayer3.
We have also assimilated substantial experience in sub-100 nm MTJ fabrication and process integration with in-house development of a 1Mb STT-MRAM CMOS chip, and thereby established a detailed understanding of variations arising from the fabrication process. To further mitigate memory read and write errors, we have invested extensive efforts on designing error correction codes (ECCs) for NVM in recent years.
- J. Lourembam et al., Appl. Phys. Lett. 113, 022403 (2018)
- J. Lourembam et al., AIP Advances, 8, 055915 (2018)
- M. Zeng et al., Appl. Phys. Lett. 113, 192404 (2018)
- J. Lourembam et al., Phys. Rev. Appl. 10, 044057 (2018)
- A. Okada et al. PNAS 114, 3815 (2017)
- Magnetoelectric device, method for forming a magnetoelectric device, and writing method for a magnetoelectric device.
(US patent:US9601174B2 )
- Magnetoresistive device and a writing method for a magnetoresistive device.(US patent:US9058885B2)
- Methods and circuit arrangements for determining resistances.(US patent:US9697894B2)
- Memory device with soft-decision decoding.(US patent:US8917540B2)
Dr. Lim Sze Ter