Seminar on ESD (Electrostatic Discharge) Failure Mechanisms and Models

Date: 30 Jun 2011 - 30 Jun 2011

Venue: SIMTech Auditorium, Tower Block, Level 3

Electrostatic discharge (ESD) is one of the most prevalent threats to electronic device reliability. ESD can arise from electrical charge being transferred from a charged body (e.g. human body) to a device. It can also arise from electrical charge built up in a device (e.g. by electrical field induction) discharging to a metal surface. The process can result in a very high current passing through the device within a very short period of time, generating either gross or latent damage to the device through complex electrothermal processes. It has been estimated that ESD-related losses run into billions of dollars annually worldwide. This will worsen with the continued scaling of the CMOS technology and emergence of new devices with low ESD tolerance. A good understanding of the ESD failure mechanisms and models will help in designing robust ESD protection devices, identifying ESD weak points in circuit or device design, and localisation and explanation of ESD-induced defects during failure analysis. In this seminar, world renowned ESD expert Dr Steven Voldman will share with us his insight into the physics of ESD failures using a case-study approach. He will adopt a generalist perspective followed by explanation of the failure mechanisms in specific technologies, circuits and systems. He will also propose practical technology or circuit solutions. Speakers from SIMTech and the industry will also complement the discussion by covering the principles and methodology for ESD testing, photon emission microscopy and nanoscopy, board-level ESD simulation as well as ESD control in the laboratory and production environment.  Programme
 8.15am        Registration, Morning Refreshemnt & Networking
 9.00am        Welcome Address
 9.05am        Very-Fast Transmission Line Pulse (VF-TLP)& Charged Device Model (CDM) ESD Testing by Dr Lai Weng Hong, SIMTech
 9.35am        Scanning Near-field Optical Microscopy and Photon Emission Microscopy by Dr Isakov Dmitry, SIMTech
10.10am       Break
10.15am       ESD Failure Mechanisms and Models (Part I) by Dr Steven Voldman
11.50am       Introduction of SIMTech's Graduate Diploma in Precision Measurements and Characterisation by Dr Xu Jian, SIMTech
12.00pm       Lunch and Networking
 1.00pm        ESD Failure Mechanisms and Modelling (Part II) by Dr Steven Voldman
 2.30pm        Break
 2.35pm        Board-level ESD Simulation by Dr Klaus Krohne, Manager, CST
 3.05pm        ESD Control in the Lab and Production Environment by Mr Inderjit Singh, Director, Cesstech
 3.45pm        ESD Lab Demonstration
 4.15pm        End of Seminar 

ESD Failure Mechanisms and Models by Dr Steven Voldman
Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.  This tutorial studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The tutorial is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology. The course will contain: 
• Failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems;  
• Electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR),  tunneling magneto-resistor (TMR),  devices; micro electro-mechanical (MEM) systems, and  photo-masks and reticles;  
• Practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis);  
• The failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, illustrated with case studies of the elements, circuits and system-on-chip (SOC) in today’s products.  

Very-Fast Transmission Line Pulse (VF-TLP) & Charged Device Model (CDM) ESD Testing by Dr Lai Weng Hong, SIMTech
The semiconductor industry is scaling down device dimensions and operating voltages. New devices with very low ESD robustness are also emerging. However, the ESD voltage that semiconductor devices are subjected to, is not scaling down. In fact, there is increasing demand for devices to operate in ‘harsh environment’. Thus, ESD will pose a serious and growing challenge to the robustness and reliability of integrated circuits (ICs). In particular, studies have shown that the Charged Device Model (CDM) ESD events account for more than half of the ESD-related failures in the modern IC production processes and applications. The robustness of packaged IC parts can be evaluated using the CDM ESD tester while that for CDM ESD protection devices at the wafer level can be evaluated by the Very-Fast Transmission Line Pulse tester. The objective of this discussion is to explain the principles and methodology of the CDM and VFTLP testing processes. This will be complemented by an ESD lab tour to reinforce the learning. 

Scanning Near-field Optical Microscopy (SNOM) and Photon Emission Microscopy (PEM) by Dr Isakov Dmitry, SIMTech
Photon generation in silicon semiconductor devices is a well known phenomenon and it is used as one of the primary fault localization techniques in failure analysis. The localisation is usually achieved by comparing emission pattern from good and faulty devices. Abnormal emissions or absence of the emissions in the faulty device is a good indicator of the fault location. The main limitation of conventional Photon Emission Microscopy (PEM) is that it is a far-field optical technique and thus, its spatial resolution is limited by diffraction to a half of a detected wavelength. In real systems with aberrations and other imperfections this limit leads to spatial resolution on the order of 1 mm. Such poor resolution makes PEM becomes less useful for the semiconductor industry that is already shifting manufacturing towards 32 nm technology node. That is why our group is focused on the development of Photon Emission Nanoscopy (PEN) that can achieve detection of photon emissions with spatial resolution below 50 nm. PEN is based on the near-field detection principle that allows surpassing the diffraction limit.  
This talk will describe the principles of far-field PEM and near-field PEN and there technical implementation in SIMTech. It will also highlight the recent results recorded on a variety of silicon devices, including silicon p-n junction and FinFET. The discussion will also include limitations of the current PEN set-up and suggest possible solutions for these limitations.   

Board-level ESD Simulation by Dr Klaus Krohne, CST
The importance of ESD protection design at the board level is escalating, with the rising sensitivity of components due to increases in transistor density and reductions in die size. By employing transient co-simulation, the physical geometry can be solved in combination with circuit components enabling non-linear effects to be included. ESD current paths can be visualised and the performance of transient protection devices assessed. The ESD event can be simulated using a circuit representation of the human body model (HBM) output, or using a more sophisticated ESD gun model. This talk will leverage on a commercial tool for ESD analysis and include a live demonstration.  

ESD Control in the Lab and Production Environment by Mr Inderjit Singh, Cesstech
Having established failure modes and damage thresholds – how can one then put necessary ESD controls in place in the production environment to ensure that damage due to real world ESD events is minimised. This session serves to highlight some of the necessary ESD critical control points that cover proper workstation / materials / tools grounding, operator / personnel ESD safety and protection, packaging considerations, ionization and ESD event monitoring. The session will cover hands-on demonstrations and samples of some of these critical ESD controls will be made available as well. 

About the Speakers
Dr Steven H. Voldman is a recipient of the IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology” in 2003, and the ESD Association Outstanding Achievement Award, in 2007. He has a B.S. in engineering science from the University of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS in engineering physics (1986) and a Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow program. Dr Voldman was Chairman of the SEMATECH ESD Working Group from 1995 to 2000, to establish a national strategy for ESD in the United States. He was also the first ESD Association Technology Roadmap Chairman. He has served as an ESD Association Board of Director  (2000 to 2006), and an Appointed ESDA Board of Director (2006-2007).  He has been an EOS/ESD Symposium Technical Program Chairman, Vice Chairman, and General Chairman from 2000-2002; and, presently serving as the ESD Symposium Vice Chairman (2008); and General Chairman (2009). In the ESD Association Device Standards Development  he has served on the HBM, MM, CDM, TLP, VF-TLP, CDE, and HMM Work Groups. He has been the ESDA Chairman of the TLP standards committee which developed both the TLP and very fast transmission line pulse (VF-TLP) standard practice documents, released in 2004 and 2008, respectively. He presently serves on the ESDA Standard Committee body, the ESDA Education Committee, is an ESD Threshold Magazine Associate Editor, and ESD Technology Roadmap team.

Dr Steven H. Voldman has provided tutorials on ESD failure mechanisms to the International Reliability Physics Symposium (IRPS), the Electrical Overstress / Electrostatic Discharge (EOS/ESD) Symposium, the Taiwan Electrostatic Discharge (T-ESD) Conference, and the International Physical and Failure Analysis (IPFA) in Singapore.  Voldman established the “ESD on Campus” program to bring ESD lectures and interaction to university faculty and students in the United States, Europe, Taiwan, Singapore, Malaysia, Philippines, China and Thailand; including the MIT Lecture Series, Stanford University, University of Vermont, University of Illinois Urbana-Champaign, University of Wisconsin Milwaukee, University of Central Florida, University of Buffalo, Nanyang Technical University, National University of Singapore, Chulalongkorn University,  Kasetsart University, Thammasat University, Mahanakorn University, National Taiwan University, National Taiwan University of Science and Technology, National Chiao-Tung University,  Zheijang University, Shanghai Jiao-Tong University, Fudan University, Mapua Institute of Technology, and Universiti Sains Malaysia. Dr Voldman has written over 150 technical papers between 1982 and 2011. He is a recipient of over 213 issued US patents, in the area of ESD and CMOS latchup.  Dr. Voldman was recognised as a IBM Corporate Top Inventor from 2000 to 2002, and received the IBM Master Inventor Award in 2006.  He also has presented tutorials on innovation, inventing and patenting internationally. Dr Voldman is an author of the John Wiley & Sons ESD book series – the first book ESD: Physics and Devices; the second book ESD: Circuits and Devices, and the third book ESD: RF Technology and Circuit, fourth book  Latchup, fifth book,  ESD Failure Mechanisms and Models, and sixth text ESD Design and Synthesis In addition, he is a contributor to the books Silicon Germanium: Technology, Modeling and Design, and Nanoelectronics.

Dr Klaus Krohne received his Diploma in Electrical Engineering from the Darmstadt University of Technology, Germany in 2002 and his Doctor of Sciences from the Swiss Federal Institute of Technology (ETH) in Zurich, Switzerland in 2007. From 2007 to 2009 he was a Researcher with the A*Star Institute of High Performance Computing in Singapore. His research interest was in the area of electromagnetic simulation and component optimisation techniques. Since 2009, Klaus is working as a Sales and Customer Support Manager for CST (Computer Simulation Technology) in Singapore. 

Mr Inderjit Singh is presently a Director with Cesstech (S) Pte Ltd which deals with the sales & service of Cleanroom (contamination / ESD) related instrumentation and provides third party cleanroom performance testing & certification. Mr Singh has more than 20 years of experience in the field of contamination control and ESD and static charge control in Cleanrooms. His expertise and experience lie in the field of cleanroom performance testing & certification, performance of ESDC testing & audits and the sales, service, technical management and selection of ESD products like ionizers & ESD management tools inclusive of ESD testing of flooring / enclosures / worksurfaces, tools and equipment etc within the Data Storage, Semiconductor, General Electronics & Solar industries. He has a Degree in Engineering from National University of S’pore and a MBA from  the University of Hull . He is a member of the EOS/ESD Association, NEBB, NARTE Inc and a Senior Member of the IEST (Institute of Environmental Sciences and Technology).  Professionally he is a NEBB (National Environmental Balancing Bureau) certified Cleanroom performance testing supervisor, having passed theory and practical examinations conducted by NEBB (National Environmental Balancing Bureau) in Apr 1994. He is also a NARTE (National Association of Radio and Telecommunications engineers) certified ESD engineer (Certification No : #328), and has also completed a course on “ESD Program Development & Assessment based on ANSI/ESD S20.20-1999”, designed specially for consultants, program managers and auditors. He has been a NARTE certified ESD engineer for 10 years and NEBB certified CPT supervisor for 17 yrs now.  

Dr Lai Weng Hong is a Scientist at the Singapore Institute of Manufacturing Technology (SIMTech). His research interest is in ESD design, modeling, testing and failure analysis. Prior to joining SIMTech, he has more than 13 years of cross-disciplinary experience in the semiconductor industry in wafer processing, device modeling, and IO/ESD library development across various technology nodes. He holds a PhD in Electrical Engineering and B.Eng. (Hons) in Electrical Engineering from the National University of Singapore (NUS). He is the author of one invited paper, author and co-author of 11 research papers and two patents.

Dr Dmitry Vladimirovich Isakov has joined Singapore Institute of Manufacturing Technology (SIMTech) since 2008 as Assistant Research Scientist, where he focuses on nanometric measurement and characterisation of semiconductor devices. He received his M.Sc. from the Department of Physics, Moscow State University, Russia in 2004. In 2010 he received Ph.D degree from the Department of Electrical and Computer Engineering, National University of Singapore, Singapore. His Ph.D research was focused on development of Scanning Near-field Photon Emission Microscopy (SNPEM). SNPEM targets localisation and characterisation of faults in semiconductor devices with resolution beyond 100 nm. Application of SNPEM to FinFETs was recognised by international semiconductor failure analysis community and awarded best paper at ISTFA2009 in Portland, USA. 

Who Should Attend
Design,  QRA and ESD Programme Managers, Engineers, Researchers, Academic Staff and Students. 

Registration Fee: S$50 per participant
SMS member: S$40 per participant
(Registration fee is inclusive of 7% GST)

To reserve a place, please register online before 29 June 2011.

All cheques and bank drafts must be made payable to 'Singapore Institute of Manufacturing Technology', crossed and marked 'A/C payee only'. The seminar title should be written on the back of the cheque. 
GST Registration No : M9-0000888-J

Contact Us
For technical enquiries, please contact : Dr Lai Weng Hong, Email:
For general enquiries and registration, please contact : Alice Koh, Email: