Events

Seminar on Innovations towards Cost Sensitive Packaging for Today's Electronic Products

Date: 28 Oct 2010 - 28 Oct 2010

Venue: SIMTech, Auditorium, Level 3, Tower Block

Introduction
As cost competition in the electronic packaging industry intensifies, industry players and researchers have to stay focus on the cost aspect, while making sure that there is no compromise on the performance of electronic packages. This half-day seminar will summarise the advancement in the electronic packaging industry, with emphasis on equipment, material and packaging innovation, having cost competitiveness.

Programme
9.00am      Registration
9.15am      Micro/nano-joining R&D capability in SIMTech by Dr Wei Jun, Joining Technology Group, SIMTech
9.45am      Evolving Wire Bonding Innovations, Trend and its Relevance to Current & Future Packaging by Mr Mohandass Sivakumar, ASM Technology
10.25am    Coffee Break
10.45am    Overview of IC Packaging Trend with Focus on Materials for Cost Competitive Packaging Technologies
                  by Mr Tan Tat Hong, Sumitomo Bakelite Singapore Pte Ltd
11.25am    Innovation in Chip Embedding Packaging Technology : eWLB by Mr Ganesh VetrivelPeriasamy, Infineon Technologies Asia Pacific
12.05pm   End of Seminar

Presentation Abstracts
Micro/nano-joining R&D capability in SIMTech by Dr Wei Jun, Joining Technology Group, SIMTech
Micro/nano-joining technology has been one of key research focus in Joining Technology Group (JTG). With the miniaturisation of devices, new generation of solder materials that are equipped with a combination of good thermal, electrical and mechanical properties is developed. Low temperature diffusion bonding lowers harsh bonding conditions for joining direct metal, dissimilar metals and hybrid material. This helps to avoid the degradation or damage of pre-fabricated devices and integrated circuitry, minimizes bonding-induced stresses after cooling, and reduces warpage issues. JTG also has good competency in the growing of carbon nanotubes (CNTs) for interconnection and devices applications.

Evolving Wire Bonding Innovations, Trend and its Relevance to Current & Future Packaging by Mr Mohandass Sivakumar, ASM Technology
Electronic packaging is one of the key enabler in the current global technology revolution. Interconnection is one of the important process in electronic packaging. Today, wire bonding is a predominantly (>85% ) used method in interconnecting the chip and substrate. It is quite certain that we use wire bonded electronic package in some way in our life. Interestingly Singapore is the world largest exporter of  wire bonder to the rest of the world. The drive towards thinner, faster, cheaper gadgets are transforming the electronic packages and wire bonding requirements.  This drive has propelled the whole wire bond eco-system to continuously evolve with new wires (Cu wire, Coated Cu Wire, High reliability Au wire, Alloyed wire), capillary with special surface textures and materials, new bond pad metallisations, continuously improving wire bonder speed and special process features in the wire bonder. This talk shall provide an overview on the recent wire bonding developments, trends, drivers, available solutions emerging challenges and opportunities for the packaging & research community.

Overview of IC Packaging Trend with Focus on Materials for Cost Competitive Packaging Technologies by Mr Tan Tat Hong, Sumitomo Bakelite Singapore Pte Ltd
A brief packaging trend will be shared. In view of continuous miniaturization and performance enhancement of advance electronics packages, innovative processes & materials becomes indispensable critical enablers to curb cost inflation.
Amongst many others, enabling technologies behind Epoxy Molding Compound for Copper wire packages & embedded Wafer Level Packages (eWLP) will be briefly examined.

Innovation in Chip Embedding Packaging Technology : eWLB by Mr Ganesh VetrivelPeriasamy, Infineon Technologies Asia Pacific
Mr VetrivelPeriasamy's presentation will cover the following areas : chip embedding packaging trends, Infineon's eWLB (embedded Wafer Level Ball Grid Array), drivers and benefits of eWLB and the process, material & reliability challenges. He will also touch on the 2nd generation eWLB development and the new opportunities in the 3rd dimension SiP application 3D eWLB.

About Presenters
Dr Wei Jun is currently the Group Manager leading the Joining Technology Group at Singapore Institute of Manufacturing Technology. He is also the Guest and Adjunct Professor at several international and local universities.
His R&D activities include micro/nanojoining, carbon nanotubes, nanostructuring, nanocomposites, advanced interconnection, microsystems and nanosystems fabrication and packaging, hermetic/vacuum sealing, low temperature wafer/substrate bonding, as well as clean energy. He is serving several international conference and professional committees. He has published more than 250 technical papers and holds more than 30 patents and technology disclosures.

Mr Mohandass Sivakumar is currently working as Technical Marketing Manager at ASM Singapore and working on wire bonding product marketing. He also leads collaboration projects with customers for wire bonding technology solutions & Cu wire bonding proliferation.  He has been with ASM Technology Singapore since 2005, prior to joining ASM he was involved in advanced packaging research & development at ASTAR – IME Singapore and worked in various sub contractor manufacturing houses in India & Singapore. In his 14 years of packaging experience, he has published more than 20 paper publications in leading journals & conferences. Siva earned a B. Eng degree from the Madras University, India and M.S from NTU Singapore.

Mr Tan Tat Hong received his Bachelor (Hons) and Masters Degrees in Mechanical Engineering from the National University of Singapore in 1994 & 1996 respectively. In 2004, he obtained a MBA (Technology Management) Degree from Nanyang Business School (NBS) of Nanyang Technological University (NTU). He joined Sumitomo Bakelite Singapore Pte. Ltd (SBS) in 1996 as an R&D Engineer and is currently the General Manager at the Electronics Device Material Research Laboratory (EDLS) of SBS. He and his team at EDLS perform Application Research and supports regional Customer Development of Epoxy Molding Encapsulant (EME) and Clear Resin for Mounting (CRM). He holds 12 patents in Japan and Singapore with a few more pending.

Mr Ganesh.VetrivelPeriasamy is working in Infineon Technologies Asia Pacific Pte Ltd., Singapore as Senior Staff Engineer focusing on technology development for next generation embedded Wafer Level BGA’s [eWLB]. He has 14 years of experience in the semiconductor industry especially in technology project management in developing advanced electronic packages. Before joining Infineon, he was working in Institute of Microelectronics, Singapore, leading focus industry and consortium projects. He has authored/co-authored more than 20 technical papers in leading conferences, magazines and journals and to date has 3 US patents awarded. He earned his Master’s degree from NUS, Singapore and B.Engrg from Bharathiar University, India.

Registration
To reserve a seat for this seminar, please register online. Closing date for registration : 27 October 2010

Contact Us
For Technical Enquiries  : Dr Effie Chew. Email : effiechew@SIMTech.a-star.edu.sg
For General Enquiries : Ms Samantha Sukiyama Chan. Email : chanskf@SCEI.a-star.edu.sg