Venue: Auditorium, Level 3, SIMTech Tower Block, 71 Nanyang Drive, Singapore 638075
ESD (electrostatic discharge) failure mechanisms continue to impact semiconductor components and systems as technologies continue to scale from micro- to nano-electronics. With the evolution and scaling of technology, ESD failure mechanisms occur in all technologies. In this lecture, a wide variety of technology from photomasks to advanced CMOS development will be discussed. The lecture will also take a look at electrical overstress, electrostatic discharge, and latchup from the semiconductor device, circuit, semiconductor chips to systems.
The presentation will provide a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The lecture takes a unique twist by covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology. This lecture will emphasize on failure analysis, electro-thermal models, and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, Silicon on Insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, Gallium Arsenide (GaAs), magneto-resistive (MR) ,giant magneto-resistors (GMR), tunneling magneto-resistor (TMR), photo-masks and reticles, to micro-electromechanical systems (MEMs). For CMOS technology, modern CMOS technology to FinFET technology and its implications to ESD protection in the future will be discussed. In the area of MEMs, the lecture will present the discussions on all types of future applications from micro-motors, RF MEM switches, to micro-mirror arrays. This lecture will be based on the newly released book ESD: Failure Mechanisms and Models.
Who Should Attend
Engineers, researchers, lecturers, students and ESD professionals/co-ordinators who wish to understand how to implement a highly effective ESD programme in electronics manufacturing.
9.45 am – 10.00 am Registration
10.00 am – 11.30 am Lecture by Dr Steven H Voldman
11.30 am End
About Dr Steven H Voldman
Dr Steven H Voldman is an IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He was the recipient of the ESD Association Outstanding Contribution Award in 2007. He received his BS in Eng Science from University of Buffalo (1979); a first MS EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng Physics (1986) and a PhD EE (1991) from University of Vermont under IBM's Resident Study Fellow program.
He was a member of the IBM development for 25 years, working on Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS, Silicon Germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technology. In 2008, he was a member of the Qimonda DRAM development team, working on 70, 58 and 48 nm technology. In 2008, he worked in Hsinchu, Taiwan for Taiwan Semiconductor Manufacturing Corportion (TSMC) as part of the 45 nm ESD and latchup development team. In 2009, he is presently a Senior Principal Engineer working for the Intersil Corporation on ESD and Latchup.
He is presently General Chairman for the EOS/ESD Symposium in 2009, and is a member of the technical program committee for the Taiwan ESD Symposium, and the first International Workshop on ESD (IWESD) in Hangzhou, China. Dr Voldman was chairman of the SEMATECH ESD Working Group, from 1995 to 2000. He is presently a member of the ESD Association Board of Director, ESD Standards Chairman for Transmission Line Pulse testing, and member of the Education Committee. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 32 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr Voldman has written over 150 technical papers between 1982 and 2009. He is a recipient of over 188 issued US patents, in the area of ESD and CMOS latchup. Dr Voldman has also written articles for Scientific American and is author of the book series ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, a fourth text, Latchup, and a new fifth text, ESD: Failure Mechanisms and Models, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design.
Nanyang Technological University and IEEE Nanotechnology Chapter
This lecture is free-of-charge. Pre-registration is required. Please register online by 1 Oct (Thurs)
Technical enquiries: Mr Eric Chen Boon Khai, Senior Research Engineer, Email: bkchen@SIMTech.a-star.edu.sg
General enquiries: Ms Fong Cheng Yen, Tel: 6793 2591, Email: email@example.com