Short Course on ESD Protection for Electronic Systems and Physics of ESD in Semiconductor

Date: 05 Oct 2009 - 06 Oct 2009

Venue: Training Room 1, Tower Block, Level 3

Course Synopsis
ESD Protection for Electronic Systems
ESD (electrostatic discharge) protection on systems will be discussed. In recent years, the ESD evaluation of semiconductor chips and systems experienced an increased interest with the introduction of portable systems, handheld components, and scaling of semiconductor components
This module will cover traditional ESD models, followed by recent advancement of new model issues. Traditional semiconductor device testing models, such as human body model (HBM), machine model (MM), charged device model (CDM) will first be discussed. This will lead to recent testing techniques of transmission line pulse (TLP) and very-fast TLP (VF-TLP) standards. Environmental issues, such as humidity and temperature and  how it affects ESD phenomenon will be discussed. In addition, the module will discuss traditional issues on board design, assembly processes, and system grounding. Semiconductor manufacturing and assembly tools and methods will be discussed. The module will feature examples such as semiconductor dicing, handling tools, shipping tools, trays, carts, and conveyer belts. System level grounding, and work surfaces will be discussed. 
The next portion of this lecture is the system level ESD models and new ESD models of interest.  Growth of interest in IEC pulse testing, and ESD guns will be discussed; the concerns of the ESD gun variation and IEC model will be reviewed. The standards development of the Cable Discharge Event (CDE) model, Charged Board Event (CBE) model, and Human Metal Model (HMM) will be presented. As the boundaries between systems and chips lessen, these new ESD models will take on greater importance in future semiconductor chip and system developments.

Physics of ESD in Semiconductor
The first part of this module covers introduction on physical time constants and ESD physical pulse models. The course will focus on concepts of stability and instability from an electrical and electro-thermal perspective. Breakdown instabilities are discussed from both a time and spatial perspective which will be used in future discussion for understanding of MOSFETs and current constriction, and ballasting.  Other focus will include thermal models, thermal physics and ESD electro-thermal models.  This discussion will naturally flow into ESD physics in semiconductor devices.  The devices include diodes, resistors, bipolar transistors, silicon controlled rectifiers, and MOSFETs.  High current, high voltage and high temperature effects will be addressed. For resistor elements, the focus will be on velocity saturation effects. For bipolar transistors, limitations such as the Johnson Limit, Kirk effect and basic models will be discussed. For the silicon controlled rectifier, the focus will be on the criteria for triggering for different cases, and the general tetrode model. Holding current formulations will also be discussed. For MOSFETs, the focus will be on MOSFET current constriction, avalanche phenomenon, parasitic bipolar, and MOSFET gate-induced drain leakage phenomenon. These fundamentals will help the participants in understanding how to design semiconductor devices for VLSI applications. The course will then take a unique turn by covering the physics, the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology.  Examples will be drawn from the state-of-the-arts technologies of CMOS, BiCMOS, Silicon on Insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, silicon germanium technology, and Gallium Arsenide (GaAs). The source of the material for this part of the module will be drawn from the text, ESD: Physics and Devices.
In the second half of this module, ESD design layout and design synthesis of semiconductor chips; from ESD input node circuits to ESD power clamps will be covered. ESD circuits and chip design will be discussed, including how to design ESD circuitry for full chip protection. The focus will be on ESD input circuits, ESD power clamps, receiver networks, off-chip driver networks and other design synthesis issues. The source of the material for this part of the module will be drawn from the text, ESD: Circuits and Devices.

05 October
1:00pm    Registration for course
1.30pm    ESD protection for electronic systems Part 1
3.30pm    Tea break
3.45pm    ESD protection for electronic systems Part 2
06 October
9.00am    The physics of ESD in semiconductor Part 1
10.30am  Tea break
10.45am  The physics of ESD in semiconductor Part 2
12.30pm  Lunch
1.30pm   The physics of ESD in semiconductor Part 3
3.30pm   Tea break
3.45pm   The physics of ESD in semiconductor Part 4

About Dr Voldman
Dr Steven H VOLDMAN is an IEEE Fellow for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.”   He was the recipient of the ESD Association Outstanding Contribution Award  in 2007.  He received his BS in Eng. Science from Univ. of Buffalo (1979); a first MS EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; a MS Eng. Physics (1986) and a PhD EE (1991) from Univ of Vermont under IBM's Resident Study Fellow program.  

He was a member of the IBM development for 25 years working on Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS, Silicon Germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technology. In 2008, he was a member of the Qimonda DRAM development team, working on 70, 58 and 48 nm technology.  In 2008, he worked in Hsinchu, Taiwan for Taiwan Semiconductor Manufacturing Corportion (TSMC) as part of the 45 nm ESD and latchup development team.   In 2009, he is presently a Senior Principal Engineer working for the Intersil Corporation on ESD and Latchup.

He is presently General Chairman for the EOS/ESD Symposium in 2009, and is a member of the technical program committee for the Taiwan ESD Symposium, and the first International Workshop on ESD (IWESD) in Hangzhou, China. Dr Voldman was chairman of the SEMATECH ESD Working Group, from 1995 to 2000. He is presently a member of the ESD Association Board of Director, ESD Standards Chairman for Transmission Line Pulse testing, and member of the Education Committee.  He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 32  universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China.   Dr Voldman has written over 150 technical papers between 1982 and 2009. He is a recipient of over 188 issued US patents, in the area of ESD and CMOS latchup. Dr Voldman also has written an articles for Scientific American and  is an author of the book series ESD: Physics and Devices, ESD:Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, a  fourth text,  Latchup,  and a new fifth text, ESD: Failure Mechanisms and Models,  as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design.

Target Audience
The seminar is extremely suitable and useful for researchers, engineers and managers in the areas of
•    IC design
•    IC testing services
•    Wafer manufacturing
•    Electronic packaging
•    Electronic devices
•    Electronic QA
•    Reliability and failure analysis software

Registration Fee :
Non-SMS Member: S$321 (incl. 7% GST)
SMS Member: S$267.50 (incl. of 7% GST)
(Registration Fee includes course materials and refreshments)

For technical enquiries, please contact Dr Kok Shaw Wei at 67938505 or email to

For general enquiries, please contact Samantha Chan at 67938423 or email to