Lock pad structure for stacking multiple chips

Overview

As the demand for higher wiring connectivity and shorter distances between chips increases, 3D packaging is the most promising solution. Chip-to-chip stacking using conventional package assembly method is the most cost-effective way of making 3D packages. The current state of the art involves sequential assembly which has the drawbacks of low throughput, die shift, and solder bridging. Multiple heating of the bottom chip also results in different inter-metallic composition of the solder joints.

Our invention offers a method of stacking multiple chips that promises high throughput and other advantages, without the need for special materials or additional process.

Our Innovation

Our innovation employs the use of batch process in order to stack multi chips. This is a high throughput process with more than 100% reduction in assembly process time. This method also allows for minimized die shift during the stacking process while also allowing for uniform micro-joint composition in multi-stacks.

Potential Applications

The potential applications for this technology would be in situations applicable for 3D packaging. 3D packaging could be used in handheld, portable products, and multiple chip stacking for memory. Overall, this technology could be applied to any industry that requires the use or need to stack chips of different sizes. 

Our Value Proposition

The need for smaller form factors in products such as mobile phones, digital cameras, digital video recorders, and multimedia players fuels the market for 3D packaging solutions. Siliconware Precision Industries Co., Ltd. and Advanced Semiconductor Engineering, Inc. is witnessing increased customer demand for 3D packaging solutions for applications in NAND memory cards, complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and Bluetooth modules.

Global semiconductor sales forecasted to reach $324.1B by 2011(Frost 2009). This method is cost-effective, easily implementable using standard wafer level re-distribution process. No additional special material or process required compared to conventional spin-on/laminated type dielectric material used. Chip stacking can be achieved using conventional package assembly tools.