


ULP sensor interface: We developed a suite of design techniques to realize ultra-low-power sensor readout with low input referred noise, wide dynamic range, and small footprint for biomedical and industrial applications. Novel direct digitization architecture which converts signals from analogue to digital domain close to the signal source is developed. This digital intensive architecture is suitable for implementation in advanced process nodes to fully leverage the advantages of technology scaling.
(a) Wearable multimodal bio-signal recording system. |
(b) VCO-based Σ∆ Capacitance to Digital Converter |
Low-power RISC-V: We explore open-source RISC-V architecture as a platform to enable innovation in Edge AI. Our first RISC-V chip has been fabricated and tested in 40nm CMOS and we are expanding our custom instructions and silicon fabrics to harvest the full potential of our hardware accelerators (Fig. 1)
Cryogenic circuits for quantum technologies: We provide energy-efficient and high-speed IPs that enable large-scale quantum computing for the future. On top of conventional
AISC design and verification methodology, these circuits require specific modelling, compensation, and test set-up so that they are able to operate down to 4K temperature (Fig. 2).
Fig. 1 RISC-V processor with 512kB on-chip memory & coarse-grain reconfigurable PE array | Fig. 2 Cryogenic CMOS test chip and cryogenic measurement set-up |
Ka/K band BFIC with AiP: Tx: 27 - 31GHz, OP1dB 11.4dBm, PAE 10.5% and Phase error < 1.5° Rx: 18 - 21.2GHz, NF 2.2-2.55dB, Phase error < 1.5° (best in class). |