Packaging Design & Fabrication Services

IME offers a wide range of advanced packaging technology solutions to address the above industry needs. Our platforms include 2.5D through-silicon interposer, 3D TSV, fan-out wafer level packaging, MEMS wafer level chip-scale packaging, fine-pitch Cu pillar, chip-on-wafer (direct Cu-to-Cu) bonding, electronic-photonic integration, as well as thermal solutions.

Services

Advanced packaging turnkey solutions for industry applications
Thermo-mechanical, electrical, and thermal modeling and simulations to provide design guidelines
TSV and through-silicon interposer (TSI) fabrication for 2.5D/3D IC packaging
TSV fabrication and assembly for image sensor applications
MEMS wafer level chip-scale packaging
FOWLP demonstration for new products
FOWLP re-constructed wafers for equipment and material evaluations

Facilities

3000m² of cleanrooms
200mm and 300mm TSV engineering line
300mm FOWLP development line
Assembly and packaging lab
Package/board level reliability testing and failure analysis facilities

At IME, we offer end-to-end solutions in FOWLP & 2.5D/3D packaging and shorten the development cycle time for new applications. We also offer services in the area of wafer level fine pitch RDL of 2um/2um LW/LS, C4 solder bumping & Cu pillar micro bumping up to 20um pitch, temporary bonding & de-bonding, TSV fabrication etc.

IME’s full fledge of development line comprises state-of-the-art tools including :

PVD chamber for seed layer deposition,
PR track for photoresist coating and photo-dielectric coating,
Stepper for lithography,
Developer track, plating
Wet bench for PR stripping
Spray etcher for seed etching
Furnace for curing

Descum/etch
Flip-chip bonder for chip-to-wafer bonding
Molding tool for wafer level compression
Warpage adjuster for molding tape de-bonding and warpage adjustment
Backgrinder for wafer thinning
Laser de-bonder for carrier de-bonding
Solder jetter for solder ball attach
Wafer dicer for wafer sawing

IME provides a one-stop solution from system concept, design integration, fabrication and testing to final packaging.

PDK (built on open access) Supporting

Design Integration

Automatic guest die data import
Die on interposer floor planning
Automatic TSV placement
Interposer auto routing (constraint driven, wire sizing

Design Analysis

Package driven co-simulation with interconnects
Signal integrity analysis
Design verification
Design rule check
Connectivity rule check
Parasitic extraction (with TSV)

Research Support

Thermo-mechanical, electrical, and thermal modeling
Material/failure analysis and reliability testing