Packaging Design & Fabrication Services
Services
- Advanced packaging turnkey solutions for industry applications
- Thermo-mechanical, electrical, and thermal modeling and simulations to provide design guidelines
- TSV and through-silicon interposer (TSI) fabrication for 2.5D/3D IC packaging
- TSV fabrication and assembly for image sensor applications
- MEMS wafer level chip-scale packaging
- FOWLP demonstration for new products
- FOWLP re-constructed wafers for equipment and material evaluations
Facilities
- 3000m2 of cleanrooms
- 200mm and 300mm TSV engineering line
- 300mm FOWLP development line
- Assembly and packaging lab
- Package/board level reliability testing and failure analysis facilities
IME has a state-of-the-art 300mm advanced wafer-level packaging engineering line, which can support the development of various advanced wafer-level packaging technologies used in mobile, AI, data centre, and IoT applications.
At IME, we offer end-to-end solutions in FOWLP and 2.5D/3D packaging, shortening the development cycle time for new applications. IME is actively engaging customers in W2W and C2W hybrid bonding stacking applications.
We also offer services in the areas of wafer-level fine pitch RDL of 2 µm/2 µm LW/LS, C4 solder bumping & Cu pillar micro bumping up to 20 µm pitch, temporary bonding & de-bonding, TSV fabrication, etc.
IME’s full fledge of development line comprises state-of-the-art tools including :- PVD chamber for seed layer deposition
- PR track for coating and developing
- Stepper for lithography
- Plating (Cu, Ni, Au, SnAg)
- Wet bench for PR stripping
- Spray etcher for seed etching
- Nitrogen furnace for curing
- Oxygen plasma for descum/etch
- Flip-chip bonder for chip-to-wafer bonding
- Molding tool for wafer level compression
- Warpage adjuster for molding tape de-bonding and warpage adjustment
- Backgrinder for wafer thinning
- Laser de-bonder for carrier de-bonding
- Solder jetter for solder ball attach
- Wafer dicer for Die singulations
![[updated] 12 Inch Advanced Packaging Line](/api/media/650e9ced-466d-4238-ba24-3ca7a909c49f.png)
PDK (built on open access) Supporting
Design Integration
- Automatic guest die data import
- Die on interposer floor planning
- Automatic TSV placement
- Interposer auto routing (constraint driven, wire sizing
Design Analysis
- Package driven co-simulation with interconnects
- Signal integrity analysis
- Design verification
- Design rule check
- Connectivity rule check
- Parasitic extraction (with TSV)
Research Support
- Thermo-mechanical, electrical, and thermal modeling
- Material/failure analysis and reliability testing