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Cost Effective Interposers for Wafer-Level Heterogeneous Integration
Fan-out Wafer Level Packaging
Cross-sectional view of RDL-first FOWLP.
Advanced electronic packages need to address the growing interconnect gap between IC and PCB, achieve a high level of functional integration, and meet form-factor, power, cost, and electrical performance requirements. Fan-out wafer level packaging with fine pitch multi-level RDL and through-mold interconnects enables multi-chip integration, package-on-package (PoP), integrated passives including RLC/antenna and ultra-thin profile to meet the above requirements. IME has established a full-fledged 300mm FOWLP development line to develop novel packaging structures and process integration flows for next generation applications including mobile-AP, 5G mmWave antenna-in-package, multiple MEMS/sensors for IoT, ASIC+HBM heterogeneous integration, and automotive electronics. IME has also developed MEMS wafer level chip-scale packaging (WLCSP) platform which enables low-cost integration of capped MEMS device and CMOS ASIC device without TSVs. This packaging platform can be used for timing devices, inertial sensors, and RF MEMS packaging.
Fan-out Panel Level Packaging
Demonstrated RDL-1st flow on panel.
IME launched FOPLP consortium with 16 industry partners to demonstrate fan-out panel level packaging (FOPLP) technology. FOPLP technologies including Mold-1st and RDL-1st platforms, are being developed by working closely with various equipment manufacturers, material suppliers, fabless companies and OSATs for advanced packaging applications such as RF, baseband, mobile and 2.5D packaging. IME’s FOPLP technologies aim to leverage on existing FOWLP capabilities and overall packaging development cost benefit up to 40%.
This consortium aims to (i) develop Mold-1st and RDL-1st Fan out panel level packaging (FOPLP) integration flows on Gen 3 size panels, (ii) evaluate the various process equipment and develop the panel level processes capabilities, (iii) evaluate the materials required for FOPLP, and (iv) demonstrate large fan out package with fine pitch RDL on large panel.
Demonstrated 15 chip stacking using 20µm pitch micro bump interconnections.
High performance applications such as data centres, high performance computing, 3D image sensors, advanced memories, and artificial intelligence cube require 2.5D/3D integration based on TSV and interposer technology to meet performance and power requirements. IME has established 2.5D/3D TSV/through-silicon interposer (TSI) platform technology consisting of critical building blocks including PDK, 3D-TSV fabrication flow, thin wafer handling, as well as assembly and packaging. This has led to the successful development of end-to-end solutions for 2.5D heterogeneous integration of logic and memory, chip-on-wafer bonding for image sensors, and wafer-to-wafer bonding for high density memories. In addition, IME has developed cost-effective 2.5D/3D IC solutions through our low-cost interposer platform, active TSI, and TSV-free interposer platforms for heterogeneous integration.
Thermal Management and Cooling Solutions
Micro-jet array impinging flow simulation.
Thermal management is critical to modern electronic packages. In smartphones, data centres, and power electronics, a key challenge is to provide optimized product-oriented cooling solutions that can meet form-factor and thermal performance requirements. To meet these requirements, thermal management needs to be handled at the chip level and at the board/system level. At the chip level, IME has demonstrated active-liquid cooling technology for >350W/cm2. At the system level, smart liquid cooling can achieve cooling solutions of up to 21kW per rack for data centre application. In addition, IME is exploring the application of advanced thermal interface materials (TIM) such as 3D-graphene, for heat removal from 3D stacks achieved through TSV and PoP.
5G Packaging (Antenna-in-Package, Antenna-on-Package)
Cross section of FOWLP mmWave AiP.
Antenna-in-package (AiP) is a key integration platform for many emerging mmWave applications such as 5G, WLAN, radar, sensor and imaging, etc. Leveraging fan-out wafer level packaging (FOWLP) technology, IME has developed a unique 3D AiP for cost effective and high performance mmWave circuit. In this 3D AiP, a top mold layer is used to design the antenna elements. This top mold layer forms the antenna substrate and is optimised for maximum antenna performance without compromising the radio frequency integrated circuit (RFIC). The RFIC is embedded in the bottom mold layer which is also used to design the integrated passive circuit. A ground plane is designed to separate the top and bottom mold compound. It acts as the antenna ground plane and provides EMI shielding for the RFIC. In addition, it doubles as a heat spreader for the RFIC. The RF signals from the RFIC to the antenna are either routed to the antenna through TMV or using capacitive coupling with minimum loss. The other RFIC signals are routed through RDL to the solder bump. In this way, a typical RF transceiver AiP can be designed using just 3 RDL layers. The FOWLP AiP design is flexible, it can also be used to design end-fire antenna, and the RFIC can be either integrated face down or face up or with multi-chip integration. This helps to overcome the conventional 2D integration in which the antenna performance is limited by the proximity of the embedded RFIC and lack of design flexibility.
Copyright A*STAR Institute of Microelectronics 2019