Fan-out Wafer Level Packaging (FOWLP) for 5G mmWave Antenna-in-Package

5G base stations require proper integration of the Power Amplifier (PA) chips,  millimetre wave monolithic ICs (MMIC), passive components and millimetre wave (mmWave) antenna array to support high speed and large bandwidth communication. However, to ensure lower electrical losses,  tighter process controls are required to ensure proper matching as a manufacturing requirement to the 5G base station modules. 

To tackle these issues, IME proposes the use of Fan-Out Wafer Level Packaging (FOWLP) which allows 3D integration of the mmWave phase array antennas on top of the RF ICs within a single package. This allows components to be closely connected and ensure minimum interconnection losses. Wafer level packaging shall be used to further reduce parasitic losses and ensure adequate impedance matching. 3D FOWLP integration further allows a scalable sub-array AiP to be formed which subsequently is then used to realize the larger antenna array.

Fan-out Wafer Level Packaging (FOWLP) for Automotive mmWave Antenna-in-Package

There are increasing technology demand in the automotive industry for Advanced driver-assistance systems (ADAS) for Adaptive Cruise Control, Lane Change Assist, Automatic Emergency Brake and Forward Collision Avoidance etc. ADAS relies on inputs from multiple systems, such as automotive imaging, LiDAR, V2V/V2X communication and RADAR.

Currently the industry has widely adopted 77Ghz for the RADAR frequency which is capable of detecting various kinds of objects such as vehicles, pedestrians and infrastructures in the 30 to 250 meters range, even during poor visibility conditions. 79GHz shall be adopted by the industries for mid to short range detection. To ensure reliable and high performance for the 77GHz/79GHz RADAR at millimetre wavelength, IME proposes the use of Fan-Out Wafer Level Packaging (FOWLP) which has several key advantages such as low dielectric loss, shorter interconnects length, excellent impedance matching, higher Q inductance, significant reduction in cost/size and many more.

Advanced Intelligent Power Module (IPM) for EV/PHEV/HEV


As demand for EV/PHEV/HEV are on the rise, there are also the ever increasing demand for power modules with smaller form factor, higher power output, and higher operation temperature. Thus there is a need for the automotive industry to move from Silicon to Silicon Carbide, Si to SiC.

IME’s Advanced Intelligent Power Module (IPM) for EV/PHEV/HEV offers advance integrated double side liquid cooling and health monitoring solutions for the Inverter which converts DC from the vehicle’s batteries system to AC to drive it. Typically the inverter operates at high voltage and high current. IME technologies target to achieve 600W dissipation not only by utilizing advanced cooling packaging technologies but also careful selections of materials such as molding compound (MC), metal sintering die attach (Cu, Ag), Electrical insulating thermal interface material etc.

Currently IME is running a consortium on Advanced Intelligent Power Module (IPM) for EV/PHEV/HEV.

Electronic-Photonic Heterogeneous Integration



At the core of the digital operation of most companies and organizations is a Data Centre(DC). It hosts compute, storage, communications and related components that are assembled into servers. With the exponential growth of internet traffic, the data-handling capacity of Data Centres has been on a continuous upswing. Thus, large companies need Data Centres that host from a few 1000 up to a million servers. Such servers are referred to as Hyperscale Data Centers (HDC). HDC drive the need to bring Optical Interconnects to the Rack and Server.  Silicon Photonics has the capability of bringing Optical interconnects in optimal formfactor to the rack and server layers of a HDC. However, this requires novel electronic-photonic heterogeneous integrated packaging that allows 100s of optical Channels to be connected to Photonic and Electronic ICS and routed in and out of servers and respective racks.

IME is building electronic photonic heterogeneous integration platform based on our broad experience in Advanced Wafer Level Packaging including TSV, Through-Si-Interposers, Active Interposers, Fan-Out WLP, 3D Stacking, C2W. The goal of this platform is to enable sub-pj/bit energy consumption in Hyperscale Data Center, HPC interconnects, and low-cost solutions for optical sensing applications. The packaging platform will allow significantly improved performance at drastically lower power dissipation in pluggable transceivers, On-board-Optics, and in Co-Packaged Optical Engines. 

Chiplet
Driven by the rapidly growing needs from IoT, Automotive, Mobile and Data-Centre/High-Performance-Compute markets over the past decade, System-on-Chip(SoC) has been the go-to platform for the Semiconductor industry. As CMOS device scaling moves into sub-10nm nodes, the power-performance-area and economic advantages of the SoC are being challenged in a range of end-markets. To overcome these challenges today, the industry is looking to Heterogeneous Integration of Chiplets within a tightly integrated advanced System-in-Package (SiP). Chiplets are designed to interoperate with other Chiplets based on industry interface protocols for realizing a complex system within a tightly integrated Advanced Package such as 2.5D Through-Si-Interposer(TSI), High-Density-Fan-Out Wafer-Level Packaging(HD-FOWLP), 3D Chip-to-Wafer (C2W) or Wafer-to-Wafer (W2W) stacking.
  
 

IME Chiplets Enablement (ICE) platform has been initiated as a Singapore national program to spearhead the relevant industry ecosystem. A new Chiplet prototype centre is established along with ICE for local/global partners to lower the technical/business barriers and fast track electronic system realization from innovation to product. The ICE platform sets to augment its current strength of IME 12” advanced packaging fabrication development line with new Design Enablement solutions. The Design Enablement solutions, compressing of design kits, reference flows, reference designs and validation technologies, will be ICE research and development thrust in the next few years.

Advanced Packaging Design 
Package Design

IME advanced packaging program offer package architecture design solutions for new products together with Electrical, Thermo-Mechanical and Thermal modelling & simulations for overall package performance in terms of electrical, thermal and reliability.

 


Electrical modelling and simulations 
  • Antenna design for 5G and automotive radar applications
  • RLC parametric extraction, Signal & Power Integrity
  • EDA/ PDK reference flow for various packaging technologies
  • Electrical characterization tools
Mechanical Modelling and Simulations
  • Package parametric study
  • Wafer level & package level warpage
  • Mold flow and die shift
  • Solder joint fatigue under TC and drop test conditions
  • Material characterization capabilities
Thermal modelling and Simulation
  • Active and Passive thermal solutions
  • Board Level Thermal Performance characterization 

Assembly, Packaging and Reliability

IME have complete assembly and packaging capabilities to offer solutions for 2.5D assembly using large & thin interposer, 3D Chip stacking using Chip-to-Wafer & Chip-to-Chip Bonding, FOWLP wafer reconstruction, power module packaging and photonics Packaging. We also offer assembly and packages services such as wafer thinning, wafer sawing, wafer level compression molding, flip chip bonding using mass reflow & thermal compression bonding, solder ball attachment, wire bonding, etc.

IME have reliability test capabilities such as Temperature Cycle Test, High Temperature Storage Test (HTS),  Moisture Sensitivity Level Test (MSL), un-biased Highly Accelerated Stress Test (un-biased HAST), Drop Test and etc, which can support component level and board level testing. We also have complete failure analysis capabilities such as SEM, TEM, FIB, CSAM, X-ray etc. IME also offer reliability testing and failure analysis services.

Wafer Level Packaging

IME has state of the art 300mm advanced wafer level packaging engineering line which can support various advanced wafer level packaging technologies development such as Mold-First and RDL-First FOWLP, Passive and Active Interposers for 2.5D and Via-Middle & Via-Last TSV integration for 3D IC packaging etc used in mobile, AI, Data Centre and IoT applications. IME offer end-to-end solutions in FOWLP & 2.5D/3D packaging and shorten the development cycle time for new applications. We also offer services in the area of wafer level fine pitch RDL of 2um/2um LW/LS, C4 solder bumping & Cu pillar micro bumping up to 20um pitch, temporary bonding & de-bonding, TSV fabrication etc.


IME'S Multi-Chip 12" FOWLP Deveopment Line